View UPD17202AGF-XXX-3BE_3489941.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1997 preliminary data sheet mos integrated circuit document no. u12127ej1v0ds00 (1st edition) date published may 1997 n printed in japan m pd17202agf-011 4-bit single-chip microcontroller with lcd controller/driver and key scan circuit for fpc (front panel controller) the m pd17202agf-011 is a cmos microcontroller for the fpc (front panel controller) of a car stereo system. this microcontroller is housed in a 64-pin qfp and is provided with an lcd controller/driver and key scan circuit, enabling the reduction of the amount of wiring between the front panel of the car stereo system and the master microcontroller. features ? lcd controller/driver : can display up to 75 segments. 1/3 duty, 1/3 bias, frame frequency: 325.5 hz ? key scan circuit : can read up to 30 (5 6) keys. ? led output : 1 pin ? 3-wire serial communication mode : clock, data, and load pins ? supply voltage : v dd = 4.5 to 5.5 v ? system clock : f x = 8 mhz ordering information part number package m pd17202agf-011-3be 64-pin plastic qfp (14 20 mm, 1.0-mm pitch) the information in this document is subject to change without notice.
2 m pd17202agf-011 pin configuration (top view) 64-pin plastic qfp (14 20 mm, 1.0-mm pitch) m pd17202agf-011-3be lcd5 lcd4 lcd3 lcd2 lcd1 lcd0 gnd0 clock (int) load (p0a0) k0 (p0a1) k1 (p0a2) k2 (p0a3) k3 (p0b0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 lcd24 lcd23 lcd22 lcd21 lcd20 lcd19 lcd18 lcd17 lcd16 lcd15 lcd14 lcd13 lcd12 lcd11 lcd10 lcd9 lcd8 lcd7 lcd6 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ic (xt in ) ic (wdout) reset x out x in v dd ic (rem) ic (tmout/led) data (p0d3) blank (p0d2) ks4 (p0d1) ks3 (p0d0) ks2 (p0c3) ks1 (p0c2) ks0 (p0c1) led (p0c0) int (p0b3) k5 (p0b2) k4 (p0b1) com2 com1 com0 caph capl v lcd 2 gnd1 v lcd 1 v lcd 0 v lcdc ic(v det ) ic(v reg ) ic(xt out ) 64 63 62 61 60 59 58 57 56 55 54 53 52 20 21 22 23 24 25 26 27 28 29 30 31 32 remarks 1. ic: internally connected 2. ( ): pin names of m pd17202agf- -3be
3 m pd17202agf-011 contents 1. pin function ................................................................................................................ ............. 4 1.1 pin function list ........................................................................................................... ....... 4 2. configuration of key matrix .......................................................................................... 6 2.1 layout of key matrix ........................................................................................................ .... 6 2.2 connection of key matrix .................................................................................................... 7 3. key scan .................................................................................................................... ................ 8 3.1 key scan function ........................................................................................................... .... 8 3.2 data configuration .......................................................................................................... ..... 9 4. lcd display function ....................................................................................................... ... 10 4.1 configuration of lcd data segment and lcd panel display data ................................. 10 4.2 lcd display data configuration ........................................................................................ 12 5. serial data communication .............................................................................................. 13 5.1 serial data input ........................................................................................................... ........ 14 5.2 serial data output .......................................................................................................... ...... 15 5.3 timing chart of serial data communication ..................................................................... 16 6. application circuit example ............................................................................................ 19 7. electrical specifications (preliminary) ......................................................................... 20 8. package drawings ......................................................................................................... ........ 25
4 m pd17202agf-011 1. pin function 1.1 pin function list pin no. 1 to 25 26 58 27 28 29 to 34 35 36 37 to 41 symbol lcd24 to lcd0 gnd0 gnd1 clock load k0 to k5 int led ks0 to ks4 pin name lcd segment signal output ground clock input load input key return signal input key scan end signal output led output key source output description these pins output segment signals to an lcd panel. they are used to control the display on the lcd panel by forming a matrix with com0 through com2 (pins 62 through 64). ground pin serial communication clock input. data is input to or output from the data pin (pin 43) at the rising edge of the clock input to this pin. serial communication load input. commands are executed and the output status is cleared in synchronization with the rising edge of this pin. while this pin is high, clock input is invalid. this pin is con- nected to an internal pull-up resistor. these pins input key return signals from a key matrix. these pins are connected to an internal pull-down resistor. this pin outputs a key scan end signal to the master microcontroller. it goes high when key scanning has ended after execution of a key data output command. this pin goes low at the rising edge of the load pin (pin 28) after data has been output. while this pin is low, key data cannot be correctly output. the initial value of this pin is the low level. be sure to connect a pull-down resistor to this pin. this pin is connected to an led that is used to check connection with the master microcontroller. when this pin is low, the led lights. this pin is output depending on the led data value of display data input (data a, refer to 4.2 lcd display data configuration ). this pin is floated in the initial status. these pins output key source signals to a key matrix. i/o format cmos push- pull output C input input input cmos push- pull output n-ch open- drain output n-ch open- drain output 36 led pd17202agf-011 m 5 v
5 m pd17202agf-011 pin no. 42 43 44, 45 50, 51 52, 53 54 46 47 48 49 55 56 57 59 60 61 62 to 64 symbol blank data ic v dd x in x out reset v lcdc v lcd 0 v lcd 1 v lcd 2 capl caph com0 to com2 pin name blank input serial data i/o internally connected power supply crystal resonator reset input lcd reference voltage adjustment lcd regulator lcd boosting capacitor common signal output of lcd controller/driver description by connecting an external controller to this pin, the display of the lcd panel can be turned on/off. input level lcd display status low lights high extinguishes to control this pin, connect it to an external controller via pull-up resistor; otherwise, connect it to gnd via pull-down resistor. serial communication data i/o pin. this pin outputs data from the rising edge of the load pin (pin 28) after a key data output signal has been received, to the next rising edge; otherwise, it inputs data. connect nothing to these pins. connect these pins to gnd via pull-down resistor. short-circuit pins 52 and 53. connect this pin to v dd . this is a common power supply pin (v dd = 2.2 to 5.5 v). these pins are used to connect a crystal resonator. connect an 8-mhz ceramic oscillator or crystal resonator to these pins. the accuracy of the watch is influenced only by the oscillation frequency of the oscillator. reset input. this pin is used to adjust the reference voltage for the lcd driver. example lcd regulator pin. these pins connect a capacitor used to boost the lcd driver voltage. connect a capacitor of 0.47 m f between the capl and caph pins. these pins output the common signals of the lcd controller/driver. i/o format input n-ch open- drain output C C input C input C C C cmos 3- state output 55 56 57 59 60 0.47 f 61 m 0.47 f m 0.47 f m 0.47 f m 2 m w v lcdc v lcd 0 v lcd 1 v lcd 2 capl caph pd17202agf-011 m
6 m pd17202agf-011 2. configuration of key matrix 2.1 layout of key matrix the m pd17202agf-011 can be used to configure a key matrix of up to 30 keys, key0 through key29, by using the ks0 through ks4 pins (key source pins) and k0 through k5 pins (key return pins). keys key0 through key29 are allocated as shown below. the details of each key can be set arbitrarily. input pin (pin no.) k0 (29) k1 (30) k2 (31) k3 (32) k4 (33) k5 (34) output pin (pin no.) ks0 (37) key0 key1 key2 key3 key4 key5 ks1 (38) key6 key7 key8 key9 key10 key11 ks2 (39) key12 key13 key14 key15 key16 key17 ks3 (40) key18 key19 key20 key21 key22 key23 ks4 (41) key24 key25 key26 key27 key28 key29 remark numbers in brackets ( ) are pin numbers.
7 m pd17202agf-011 2.2 connection of key matrix an example of connection of the key matrix is shown below. momentary key = kn ksn 41 ks4 40 ks3 39 ks2 38 ks1 37 ks0 34 k5 33 k4 32 k3 31 k2 30 k1 29 k0 pd17202agf-011 m
8 m pd17202agf-011 3. key scan 3.1 key scan function key scanning is started when a key data output command is executed. the int pin (pin 35) goes high when key scanning has ended. the int pin goes low when the load pin (pin 28) goes high. figure 3-1. timing chart of key scanning ks0 ks1 ks2 ks3 ks4 int key data output command scanning ends load pin rises key data output command 1.6 - 1.9 ms (2.8 - 3.4 ms) note 50 - 60 s m note the value in brackets ( ) is when display data input + key data output is executed.
9 m pd17202agf-011 3.2 data configuration the data output by the key data output command consists of 30 bits. the contents of the output data are as shown below. figure 3-2. configuration of output data (key data output) k e y 29 k e y 28 k e y 27 k e y 26 k e y 25 k e y 24 ks4 k e y 17 k e y 16 k e y 15 k e y 14 k e y 13 k e y 12 ks2 k e y 5 k e y 4 k e y 3 k e y 2 k e y 1 k e y 0 ks0 msb lsb ?? ? 30 bits the status of the output data can be identified by the data of each bit as shown below. data status 0 key off 1 key on
10 m pd17202agf-011 4. lcd display function 4.1 configuration of lcd data segment and lcd panel display data the segments consisting of lcd0 through lcd24 pins and com0 through com2 pins correspond to the lcd panel display data as shown in the table below. table 4-1 configuration of lcd segment and table 4-2 display data table correspond to each other. any lcd display setting can be performed based on these tables. table 4-1. configuration of lcd segment common pin (pin no.) com0 (62) com1 (63) com2 (64) segment pin (pin no.) lcd0 (25) b4 a0 b0 lcd1 (24) a3 a1 b1 lcd2 (23) a4 a2 b2 lcd3 (22) b9 a5 b5 lcd4 (21) a8 a6 b6 lcd5 (20) a9 a7 b7 lcd6 (19) b14 a10 b10 lcd7 (18) a13 a11 b11 lcd8 (17) a14 a12 b12 lcd9 (16) b19 a15 b15 lcd10 (15) a18 a16 b16 lcd11 (14) a19 a17 b17 lcd12 (13) b24 a20 b20 lcd13 (12) a23 a21 b21 lcd14 (11) a24 a22 b22 lcd15 (10) b33 b38 b28 lcd16 (9) b29 a25 b25 lcd17 (8) a28 a26 b26 lcd18 (7) a29 a27 b27 lcd19 (6) b34 a30 b30 lcd20 (5) a33 a31 b31 lcd21 (4) a34 a32 b32 lcd22 (3) b39 a35 b35 lcd23 (2) a38 a36 b36 lcd24 (1) a39 a37 b37
11 m pd17202agf-011 table 4-2. display data table segment ab segment ab data name data name d40 a0 b0 d9 a31 b31 d39 a1 b1 d8 a32 b32 d38 a2 b2 d7 a33 b33 d37 a3 b3 note d6 a34 b34 d36 a4 b4 d5 a35 b35 d35 a5 b5 d4 a36 b36 d34 a6 b6 d3 a37 b37 d33 a7 b7 d2 a38 b38 d32 a8 b8 note d1 a39 b39 d31 a9 b9 d30 a10 b10 d29 a11 b11 d28 a12 b12 d27 a13 b13 note d26 a14 b14 d25 a15 b15 d24 a16 b16 d23 a17 b17 d22 a18 b18 note d21 a19 b19 d20 a20 b20 d19 a21 b21 d18 a22 b22 d17 a23 b23 note d16 a24 b24 d15 a25 b25 d14 a26 b26 d13 a27 b27 d12 a28 b28 d11 a29 b29 d10 a30 b30 note the data of segments b3, b8, b13, b18, and b23 are invalid. do not input anything for these data.
12 m pd17202agf-011 4.2 lcd display data configuration lcd display data is divided into two parts, a and b, for transmission (refer to table 4-2 display data table ). the data consists of a command (4 bits), lcd data (40 bits), and led data (1 bit), or a total of 45 bits (only when data a is transmitted. data b consists of 44 bits, excluding led data (1 bit)). figure 4-1. configuration of input data for lcd display b 3 b 2 b 1 b 0 d 40 d 39 d 38 d 3 d 2 d 1 d 0 msb lsb command (4 bits) lcd data data a or b ( 40 bits ) led data note (1 bit) note d0 (= led data) is necessary only when data a is transmitted. the status of the data can be identified by the data of each bit (0 or 1) as shown below. data status 0 extinguishers 1 lights the last 4 bits of the input data is read at the rising edge of the load pin (pin 28) as a command, and the previous data is displayed on the lcd when display data input is identified. when a low level is input to the blank pin (pin 42), the lcd display is turned on (the led also lights when data a is transmitted). when a high level is input to the blank pin, the lcd display is turned off (refer to 5.2 serial data output ). setting of the blank pin does not affect any operations other than the lcd display. the lcd display data is extinguished in the initial status (even if the blank pin is low level). the configuration of the lcd display data commands (4 bits of msb) is shown below. table 4-3. serial data i/o commands command operation b3 b2 b1 b0 0010 inputs display data (data a) 0011 inputs display data (data b) 010 outputs key data 0110 inputs display data (a) + outputs key data 0111 inputs display data (b) + outputs key data 110 outputs key data 111 outputs key data others setting prohibited : undefined
13 m pd17202agf-011 5. serial data communication the m pd17202agf-011 inputs or outputs data from or to the main microcontroller through 3-wire serial communication, using the clock (pin 27), data (pin 43), and load (pin 28) pins. figure 5-1 shows connection between the m pd17202agf-011 and main microcontroller. figure 5-1. connection between m pd17202agf-011 and main microcontroller 43 data pd17202agf-011 m 28 load data load 27 clock clock main microcontroller
14 m pd17202agf-011 5.1 serial data input the serial data is input in synchronization with the rising of the clock pin (pin 27) in the input status (the initial status is input). the last 4 bits read at the rising edge of the load pin (pin 28) are identified and processed as a command. figure 5-2 shows the timing chart of serial data input. table 5-1 lists the serial data i/o commands. figure 5-2. timing chart of serial data input clock data load d0 d1 b0 b1 b2 b3 msb lsb input data (last 4 bits are serial data input command) table 5-1. serial data i/o commands command operation b3 b2 b1 b0 0010 inputs display data (data a) 0011 inputs display data (data b) 010 outputs key data 0110 inputs display data (a) + outputs key data 0111 inputs display data (b) + outputs key data 110 outputs key data 111 outputs key data others setting prohibited : undefined remarks 1. for the data configuration of display data input, refer to 4. lcd display function . 2. for the data configuration of key data output, refer to 3. key scan . 3. execute display data input before key data output. 4. if a pulse is input to the load pin without display data input, the device does not operate. 5. the device does not operate when data other than an i/o command is input.
15 m pd17202agf-011 5.2 serial data output serial data is output in synchronization with the rising of the clock pin (pin 27) in the output status (the output status is established only when the key data output command is executed). serial data is output in the following procedure. figure 5-3 shows the timing chart of serial data output. <1> input a key data output command. <2> input a pulse to the load pin (pin 28) (the output status is established when this pin goes high). <3> input the clock (data is output in synchronization with the rising of the clock). <4> input a pulse to the load pin (the input status is established when this pin goes high). figure 5-3. timing chart of serial data output clock data load b0 b1 b2 b3 k0 k1 k28 k29 lsb msb lsb msb input data output data output status input status input status
16 m pd17202agf-011 5.3 timing chart of serial data communication the i/o timing charts of the respective pins during serial data communication are shown below. (1) serial data i/o clock data (input) data (output) load 100 ns min. 11.7 s min. m 50 ns max. 11.7 s min. m 11.5 s max. m 100 ns min. 50 s min. m 23.4 s min. m remark maximum clock frequency: 43 khz (2) on reset execution clock reset 35 ms min. 50 s min. m clock
17 m pd17202agf-011 (3) on execution of display data input clock 41 or 40 clocks + 4 clocks clock data display data + command input data load blank 2 ms min. 70 s min. less than 2 ms m 2 ms min. invalid valid valid invalid valid : the device operates within 50 m s after the value of the blank pin has been changed. if the clock is input to the clock pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 khz). invalid : the device does not operate even if the value of the blank pin has been changed. if the value of the pin is changed during this period, the device operates after the pin value has become valid. (4) on execution of key data output clock 4 clocks 1 clock data command input data load blank invalid valid valid invalid int 30 clocks key data 2 ms min. 70 s min. m 2 ms min. 70 s min. m less than 2 ms less than 100 s m 100 s min. m invalid valid : the device operates within 50 m s after the value of the blank pin has been changed. if the clock is input to the clock pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 khz). invalid : the device does not operate even if the value of the blank pin has been changed. if the value of the pin is changed during this period, the device operates after the pin value has become valid. ? ? ? ? y ? ? ? ? t blank pin ? ? ? ? y ? ? ? ? t blank pin
18 m pd17202agf-011 (5) on execution of display data input + key data clock 41 or 40 clocks + 4 clocks clock data display data + command input data load blank invalid valid valid invalid int 30 clocks key data 3.5 ms min. 70 s min. m 3.5 ms min. 70 s min. m less than 3.5 ms less than 100 s m 100 s min. m invalid valid : the device operates within 50 m s after the value of the blank pin has been changed. if the clock is input to the clock pin, however, the higher the clock frequency, the slower the operation (example: operates within 1 ms at 43 khz). invalid : the device does not operate even if the value of the blank pin has been changed. if the value of the pin is changed during this period, the device operates after the pin value has become valid. ? ? ? ? y ? ? ? ? t blank pin
19 m pd17202agf-011 6. application circuit example 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 caph capl v lcd 2 gnd v lcd 1 v lcd 0 v lcdc 64 63 62 61 60 59 58 57 56 55 54 53 52 20 21 22 23 24 25 26 27 28 29 30 31 32 lcd panel lcd24 lcd6 lcd0 lcd5 com0 com2 com1 v dd x out x in v dd v dd data blank ks4 + v dd ks0 led int k5 v dd blank clk sio load int res v dd gnd connector connector main microcontroller gnd k0 k3 load clock momentary key switch fx = 8 mhz pd17202agf-011-3be m reset
20 m pd17202agf-011 7. electrical specifications (preliminary) absolute maximum ratings (t a = 25 ?c) parameter symbol condition rating unit supply voltage v dd C0.3 to +7.0 v input voltage v i C0.3 to v dd + 0.3 v output voltage v o C0.3 to v dd + 0.3 v high-level output current i oh rem pin peak C30 ma r.m.s value C20 ma 1 pin peak C7.5 ma (other than rem pin) r.m.s value C5.0 ma all pins peak C22.5 ma (except rem pin) r.m.s value C15.0 ma low-level output current i ol 1 pin peak 7.5 ma r.m.s value 5.0 ma all pins peak 30 ma r.m.s value 20 ma operating temperature t a 20 to +75 ?c storage temperature t stg C40 to +125 ?c caution if the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be affected. the absolute maximum ratings, therefore, define the values exceeding which the product may be physically damaged. be sure to use the product without ever exceeding these values. capacitance (t a = 25 ?c, v dd = 0 v) parameter symbol condition min. typ. max. unit input capacitance c in int and reset pins 10 pf c pin other than int and reset pins 10 pf
21 m pd17202agf-011 recommended operation range (t a = e20 to +75 ?c) parameter symbol condition min. typ. max. unit supply voltage v dd0 where system clock is f x = 4 mhz 2.2 3.0 5.5 v v dd1 where system clock is f x = 8 mhz 4.5 5.0 5.5 v system clock oscillation frequency f x 1.0 4.0 8.0 mhz 10 9 8 7 6 5 4 3 2 1 0.5 (mhz) 023456(v) 2.2 4.5 5.5 system clock: f x f x vs v dd suppl y volta g e: v dd operation guaranteed range
22 m pd17202agf-011 system clock oscillation circuit characteristics (t a = e20 to +75 ?c, v dd = 2.2 to 5.5 v) oscillator recommended parameter condition min. typ. max. unit constants ceramic oscillation frequency 1.0 4.0 8.0 mhz resonator note 1 (f x ) note 2 oscillation stabilization after v dd has reached 4 ms time note 3 min. value of oscillation voltage range crystal oscillation frequency 1.0 4.0 8.0 mhz resonator note 1 (f x ) note 2 oscillation stabilization v dd = 4.5 to 6.0 v 10 ms time note 3 30 ms notes 1. use of the ceramic resonator and crystal resonator shown on the next page is recommended. 2. the oscillation frequency only indicates the characteristics of the oscillation circuit. for the instruction execution time, refer to recommended operation range . 3. the oscillation stabilization time is the time required for oscillation to stabilize after v dd application or release of the stop mode. caution when using the system clock oscillation circuit, wire the portion indicated by the dotted lines in the above figures to avoid adverse influence from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with any other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. ? always keep the ground point of the capacitor of the oscillation circuit at the same potential as gnd. do not ground the capacitor to a ground pattern through which a high current flows. ? do not extract signals from the oscillation circuit. x in x out x in x out
23 m pd17202agf-011 recommended oscillator ceramic resonator external oscillation voltage manufacturer part number capacitance (pf) range (v) remark c1 c2 min. max. murata mfg. co., ltd. csa3.58mg 30 30 2.0 6.0 csa4.00mg 30 30 2.0 6.0 csa4.19mg 30 30 2.0 6.0 cst3.58mgw unnec- unnec- 2.0 6.0 capacitor- cst4.00mgw essary essary 2.0 6.0 contained type cst4.19mgw 2.0 6.0 kyocera corp. kbr3.58ms 33 33 2.0 6.0 kbr4.0ms 33 33 2.0 6.0 krb4.19ms 33 33 2.0 6.0 toko ceramic co. ltd. crhf4.00 18 18 2.0 6.0 daishinku corp. prs0400bcsan 39 33 2.0 6.0 crystal resonator frequency external oscillation voltage manufacturer (mhz) retainer capacitance (pf) range (v) remark c1 c2 min. max. kinseki corp. 4.0 hc-49u-s 22 22 2.0 6.0 external circuit example x in x out c1 c2
24 m pd17202agf-011 dc characteristics (v dd = 3 v, t a = e20 to +75 ?c, f x = 4 mhz) parameter symbol condition min. typ. max. unit low-voltage detection voltage v det r = 2.2 m w 1.3 2.0 2.9 v high-level input voltage v ih1 reset, int pins 0.8 v dd v dd v v ih2 other than reset, int pins 0.7 v dd v dd v low-level input voltage v il1 reset, int pins 0 0.2 v dd v v il2 other than reset, int pins 0 0.3 v dd v high-level input current i ih1 int pin v ih = v dd 0.2 m a i ih2 reset pin v ih = v dd 0.2 m a i ih3 p0a through p0d pins v ih = v dd 0.2 m a low-level input current i il1 int pin v il = 0 v C0.2 m a i il2 reset pin v il = 0 v C0.2 m a w/o pull-up resistor i il3 v il = 0 v C30 C60 C120 m a w/pull-up resistor i il4 p0a, p0b pins v il = 0 v C0.2 m a w/o pull-up resistor i il5 v il = 0 v C8 C15 C30 m a w/pull-up resistor i il6 p0c, p0d pins v il = 0 v C0.2 m a high-level output current i oh1 p0a, p0b pins v oh = v dd C 0.3 v C0.6 C2.0 C4.0 ma i oh2 rem pin v oh = v dd C 2.0 v C7.0 C15.0 C25.0 ma i oh3 led pin v oh = v dd C 0.3 v C0.3 C1.0 C2.0 ma low-level output current i ol1 p0a, p0b pins v ol = 0.3 v 0.5 1.5 2.5 ma i ol2 p0c, p0d pins v ol = 0.3 v 0.5 1.5 2.5 ma i ol3 rem pin v ol = 0.3 v 0.5 1.5 2.5 ma i ol4 led, wdout pins v ol = 0.3 v 0.5 1.5 2.5 ma supply current i dd1 operating mode 0.6 1.5 ma i dd2 halt mode 0.5 1.5 ma v lcdc voltage v lcdc v dd = 3 v, t a = 25 ?c, r1 = r2 = 1 m w 0.5 0.6 0.7 v lcd output voltage variable range v lcd0 external variable resistor (0 to 2.2 m w ) 0.8 1.8 v doubler output voltage v lcd1 c1 to c4 = 0.47 m f 1.9 v lcd0 2 v lcd0 v tripler output voltage v lcd2 c1 to c4 = 0.47 m f 2.85 v lcd0 3 v lcd0 v common output current i com v ds = 0.2 v 30 m a segment output current i lcd v ds = 0.2 v 5 m a ac characteristics (t a = C20 to +75 ?c, v dd = 3 v) parameter symbol condition min. typ. max. unit int high-, low-level widths t ioh 50 m s t iol 50 m s reset low-level width t rsl 50 m s
25 m pd17202agf-011 8. package drawings 64 pin plastic qfp (14 20) item millimeters inches g q f 1.0 0.125?.075 1.0 s 0.039 0.005?.003 0.039 s64gf-100-3b8, 3be-3 note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. 3.0 max. 0.119 max. d 17.2?.2 0.677?.008 r5 ? 5 ? b 20.0?.2 0.787 +0.009 ?.008 a 23.2?.2 0.913 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 j 1.0 (t.p.) 0.039 (t.p.) i 0.20 0.008 h 0.40?.10 0.016 +0.004 ?.005 p 2.7 0.106 n 0.10 0.004 l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 +0.004 ?.003 k 1.6?.2 0.063?.008 +0.10 ?.05 detail of lead end i j f g h q r p k m l n m 51 52 32 64 1 20 19 33 a b cd s
26 m pd17202agf-011 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
27 m pd17202agf-011 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd17202agf-011 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

▲Up To Search▲

Price & Availability of UPD17202AGF-XXX-3BE

	To Download UPD17202AGF-XXX-3BE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .